摘要: Area-efficient 4/spl times/ charge pumps based on the cross-coupled structure that uses V/sub dd/-2V/sub dd/ outputs alternately to reduce number of power devices and capacitors are presented. Compared with conventional designs, our best design can save two transistors, one capacitor, level shift circuits. An integrated pump is then designed deliver 100 /spl mu/A at 9 V using a 0.8-/spl mu/m AMS high-voltage CMOS process. The topology be extended 2n/spl pumps, 6/spl also fabricated tested demonstrate validity extension.
harvard.edu
sci-hub.se 参考文章(9)
J.F. Dickson, On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique IEEE Journal of Solid-State Circuits. ,vol. 11, pp. 374- 378 ,(1976) , 10.1109/JSSC.1976.1050739
Y. Moisiadis, I. Bouras, A. Arapoyanni, A CMOS charge pump for low voltage operation international symposium on circuits and systems. ,vol. 5, pp. 577- 580 ,(2000) , 10.1109/ISCAS.2000.857500
Tianrui Fing, Wing-Hung Ki, Mansun Chan, Area efficient CMOS integrated charge pumps international symposium on circuits and systems. ,vol. 3, pp. 831- 834 ,(2002) , 10.1109/ISCAS.2002.1010353
Ming Zhang, N. Llaser, F. Devos, Integrated multivalue voltage-to-voltage converter international conference on electronics circuits and systems. ,vol. 1, pp. 335- 338 ,(1999) , 10.1109/ICECS.1999.812291
Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh, An experimental 1.5-V 64-Mb DRAM IEEE Journal of Solid-state Circuits. ,vol. 26, pp. 465- 472 ,(1991) , 10.1109/4.75040
Chi-Chang Wang, Jiin-Chuan Wu, Efficiency improvement in charge pump circuits IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 852- 860 ,(1997) , 10.1109/4.585287
P. Favrat, P. Deval, M.J. Declercq, A high-efficiency CMOS voltage doubler IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 410- 416 ,(1998) , 10.1109/4.661206
G.A. Rincon-Mora, P.E. Allen, A low-voltage, low quiescent current, low drop-out regulator IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 36- 44 ,(1998) , 10.1109/4.654935
S. Basu, G.C. Temes, Simplified clock voltage doubler Electronics Letters. ,vol. 35, pp. 1901- 1902 ,(1999) , 10.1049/EL:19991306