作者: Shashank Nemawarkar , Mark A. Bordogna , Hong Wan , Paul S. Bedrosian , Gregory E. Beers
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摘要: A network processor is described that includes a reference clock module for providing an at least substantially low-jitter, low-wander signal. In one or more embodiments, the digital phase locked loop configured to attenuate wander noise portion from The also analog communicatively coupled and receive signal loop. jitter having first frequency characteristic provide transceiver second