作者: Marcia G. M�ndez-Rivera , Alberto Valdes-Garcia , Jose Silva-Martinez , Edgar S�nchez-Sinencio
DOI: 10.1007/S10836-005-6351-Y
关键词:
摘要: This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response harmonic distortion characterizations of integrated device-under-test (DUT) through a digital off-chip interface. External instrumentation is avoided, reducing test time cost. The proposed on-chip scheme uses synthesizer simple signal generator synchronized with switched capacitor bandpass filter. A general methodology for use this structure in functional verification DUT also provided. circuit-level design experimental results prototype standard CMOS 0.5 ?m technology are presented to demonstrate feasibility BIT technique.