Mitigation of gate to contact capacitance in CMOS flow

摘要: Sidewall spacers that are primarily oxide, instead of nitride, formed adjacent to a gate stack CMOS transistor. Individual sidewall situated between conductive electrode the and contact As such, capacitance can develop contact, depending on dielectric constant interposed spacer. Accordingly, forming out which has lower than mitigates otherwise these features. Such is undesirable, at least, because it inhibit transistor switching speeds. fashioning as described herein mitigate yield loss by reducing number devices have unsatisfactory speeds and/or other undesirable performance characteristics.