A Hard Decision LDPC Decoder Implementation for Error Correction of NAND Flash Memory

摘要: We implemented a decoder for low-density paritycheck (LDPC) codes intended NAND flash memory error correction. Since the input is given as binary valued signal, hard-decision bit flipping based decoding algorithm used. To simplify hardware, circular shiftregister partially parallel architecture employed. With this architecture, it very easy to increase throughput or reduce power consumption by raising factor. The decoder, which employs (4161, 3431) projective geometry-based LDPC code, operates at 400 Mbit/s with factor of 32. Synthesized using 0.25㎛ CMOS technology, proposed consumed 208 ㎽ 2.5 V supply.