Reconfigurable logic embedded architecture of support vector machine linear kernel

摘要: Support Vector Machine (SVM) is a linear binary classifier that requires kernel function to handle non-linear problems. Most previous SVM implementations for embedded systems in literature were built targeting certain application; where analyses done through comparison with software only. The impact of different application datasets towards hardware performance not analyzed. In this work, we propose parameterizable architecture fully pipelined. It prototyped and analyzed on Altera Cyclone IV platform results are verified equivalent model. Further analysis determining the effect number features support vectors architecture. From our proposed implementation, determine maximum operating frequency amount logic resource utilization, whereas determines on-chip memory usage also throughput system.