System for simplifying the programmable memory to logic interface in FPGA
作者： Ankur Bal
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摘要: A system for simplifying the programmable memory-to-logic interface in field gate arrays (FPGAs) is provided. An may be used to isolate general purpose routing architecture intra-programmable logic blocks (PLBs) from random access memory (RAM) address lines, data and control lines. The PLBs input-output resources of FPGA embedded (or RAM) using dedicated direct interconnects. Certain these interconnects originate vicinity RAM. remainder run between (IO) pads/routing RAM blocks. bus also provided combine memories emulate larger This provides interconnection among isolated PLB resources.
lens.org 参考文章(14)
Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Om P. Agrawal, Claudia A. Stanley, Kerry A. Ilgenstein, SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES ,(2000)
Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Om P. Agrawal, Dual port SRAM memory for run time use in FPGA integrated circuits ,(1997)
Christopher W. Jones, Memory in a programmable logic device ,(1995)
Michael R. Butts, Stephen P. Sample, Kevin A. Norman, Rakesh H. Patel, Look-up table based logic element with complete permutability of the inputs to the secondary signals ,(1995)
Philip M. Freidin, Edmond Y. Cheung, Charles R. Erickson, Tsung-Lu Syu, Synchronous dual port RAM ,(1996)
T.-C. Ong, P.K. Ko, C. Hu, The EEPROM as an analog memory drive IEEE Transactions on Electron Devices. ,vol. 36, pp. 1840- 1841 ,(1989) , 10.1109/16.34250
K. Kawana, H. Keida, M. Sakamoto, K. Shibata, I. Moriyama, An efficient logic block interconnect architecture for user-reprogrammable gate array IEEE Proceedings of the Custom Integrated Circuits Conference. ,(1990) , 10.1109/CICC.1990.124842
A. Cremonesi, F. Maloberti, G. Torelli, C. Vacchi, An 8-bit two-step flash A/D converter for video applications custom integrated circuits conference. ,(1989) , 10.1109/CICC.1989.56700
K. Levitt, W. Kautz, Cellular arrays for the parallel implementation of binary error-correcting codes IEEE Transactions on Information Theory. ,vol. 15, pp. 597- 607 ,(1969) , 10.1109/TIT.1969.1054347