Word-wise processing for reed-solomon codes

摘要: A word-wise encoder circuit that processes word formatted data blocks in response to a clock signal and generates redundancy accordance with an 8 bit symbol code. The is provided two parallel paths, each receiving one of the respective bytes halves received words during period implement code signal. replicates, period, state registers standard sequential after consecutive have been processed byte clock. In preferred embodiment, used Reed-Solomon integrity this example, appended associated temporarily stored block buffer memory within channel provide mechanism for detecting errors caused by buffer. reduced hardware implementation disclosed wherein special choice generator polynomial Galois field representation allows multiplier be eliminated. per longest propagation path traverses adders.