Hardware Implementation of four byte per clock RC4 algorithm.

摘要: In the field of cryptography till date 2-byte in 1-clock is best known RC4 hardware design [1], while 1-byte [2], and 3 clocks [3][4] are implementation. The algorithm in[2] considers two consecutive bytes together processes them 2 clocks. [1] a pipelining architecture [2]. 3-clocks too much modular clock hungry. this paper considering algorithm, as it is, simpler providing higher throughput proposed which 6 different has been proposed. 1, processed 1-clock, dynamic KSA-PRGA Design 1. can process byte single clock, where 4 Dynamic 3. 5 parallelization compute clock. maturity terms throughput, power consumption resource usage, achieved from 1 to 6. encryption decryption designs respectively embedded on FPGA boards co-processor hardware, communication between performed using Ethernet.