ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis
作者： Levent Aksoy , Eduardo Costa , Paulo Flores , Jose Monteiro
DOI: 10.1109/ICECS.2006.379897
关键词:
摘要: In this work two heuristic algorithms are presented for the problems of optimization area and under a delay constraint in digital filter synthesis. The heuristics search solution on combinational network that represents covering problem using greedy method partial term selection. methods start from outputs towards inputs each coefficient. This top-down approach considers much larger space than existing bottom-up algorithms. We present results wide range instances compare them with exact prominent demonstrate solutions obtained by proposed extremely close to significantly better
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sci-hub.se 参考文章(11)
E. da Costa, P. Flores, J. Monteiro, Maximal sharing of partial terms in MCM under minimal signed digit representation european conference on circuit theory and design. ,vol. 2, pp. 221- 224 ,(2005) , 10.1109/ECCTD.2005.1523033
In Cheol Park, Hansoo Kim, Hyeong Ju Kang, FIR filter synthesis algorithms for minimizing the delay and the number of adders international conference on computer aided design. pp. 51- 55 ,(2000) , 10.5555/602902.602915
A.G. Dempster, M.D. Macleod, Use of minimum-adder multiplier blocks in FIR digital filters IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 42, pp. 569- 577 ,(1995) , 10.1109/82.466647
Anup Hosangadi, Farzan Fallah, Ryan Kastner, Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions asia and south pacific design automation conference. ,vol. 1, pp. 523- 528 ,(2005) , 10.1145/1120725.1120953
R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, D. Durackova, A new algorithm for elimination of common subexpressions IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 18, pp. 58- 68 ,(1999) , 10.1109/43.739059
Levent Aksoy, Eduardo Costa, Paulo Flores, Jose Monteiro, Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming design automation conference. pp. 669- 674 ,(2006) , 10.1145/1146909.1147079
Hyeong-Ju Kang, In-Cheol Park, FIR filter synthesis algorithms for minimizing the delay and the number of adders IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 48, pp. 770- 777 ,(2001) , 10.1109/82.959867
J. Monteiro, P. Flores, E. Costa, An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications international conference on computer aided design. pp. 13- 16 ,(2005) , 10.5555/1129601.1129607
Richard I Hartley, None, Subexpression sharing in filters using canonic signed digit multipliers IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 43, pp. 677- 688 ,(1996) , 10.1109/82.539000
In-Cheol Park, Hyeong-Ju Kang, Digital filter synthesis based on minimal signed digit representation Proceedings of the 38th conference on Design automation - DAC '01. pp. 468- 473 ,(2001) , 10.1145/378239.378564