A 128∶2048/1536 point FFT hardware implementation with output pruning

摘要: In this work, an FFT architecture supporting variable sizes, 128∼2048/1536, is proposed. This implementation a combination of 2 point Common Factor and 3 DFT. Various output pruning techniques for are discussed in terms memory control logic overhead. It shown that the used Prime as 1536 able to increase throughput by exploiting single tone with low The proposed processor implemented on Xilinx Virtex 5 FPGA. occupies only 3148 LUTs 612 kb FGPA calculates less than 3092 clock cycles pruned settings.