Power Distribution in TSV-Based 3-D Processor-Memory Stacks

摘要: Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed compared to distribute power in a 3-D processor-memory system with nine planes. Due distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated this paper. A valid space that satisfies the peak supply noise while minimizing area overhead is identified each technology. It demonstrated of distribution network via-first TSVs approximately 9% less than 2% via-middle via-last technologies. Despite drawback, based typically overdamped issue resonance alleviated. network, however, exhibits relatively low damping factor highly sensitive number decoupling capacitance.