作者: Benjamin E. Nise
DOI:
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摘要: The clock multiplying phase locked loop includes components for selectively setting a center frequency of voltage controlled oscillator (VCO) to bias the VCO operation within selected range input frequencies. To this end, is configured output signal at based upon tuning current provided VCO. Initially, set reference and feedback generated. signal, perhaps divided by N, phase-frequency detector. detector also receives having frequency. outputs an UP or DOWN indicating whether greater less than signal. A adjustment unit signals from adjusts modify reduce any difference between received VCO, unit, as well other components, operate in causing be iteratively adjusted until approximates degree resolution. At that point, disconnected detector, thus allowing multiplier (PLL). current, however, continues applied maintain such further biased Method apparatus embodiments invention are disclosed.