A 54*54-b regularly structured tree multiplier
作者： G. Goto , T. Sato , M. Nakajima , T. Sukemura
DOI: 10.1109/4.149426
关键词:
摘要: A 54-b*54-b parallel multiplier was implemented in 0.88- mu m CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but and set of partial-product-bit generators are combined into recurring block which generates seven partial-product bits compresses them to pair for sum carry signals. This used repeatedly construct an RST even wiring among blocks included wire shifters designed as units. By shifters, authors can expand level repeated cover entire adder simplifies complicated scheme. In addition, time savings, layout density increased by 70% 6400 transistors/mm/sup 2/, multiplication decreased 30% 13 ns. >
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