Stacked-NMOS-triggered SCR device for ESD-protection

摘要: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node the cascaded is usually floating during ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This used to drive upper trigger A lower transistor has that charged pulse on through coupling capacitor. When coupled turns transistors, turn silicon-controlled rectifier (SCR) integrated transistors.