作者: Xin Yang , Sakir Sezer , Shane O'Neill
DOI: 10.1109/SOCC.2014.6948969
关键词:
摘要: This paper presents a hardware solution for network flow processing at full line rate. Advanced memory architecture using DDR3 SDRAMs is proposed to cope with the match limitations in packet throughput, number of supported flows and header fields (or tuples) identifications. The described has been prototyped accommodating 8 million flows, tested on an FPGA platform achieving minimum 70 lookups per second. sufficient process internet traffic 40 Gigabit Ethernet.