Architecture and Design Methodology of 32KByte Integrated Cache Memory
作者： Akio Miyoshi , Kazuyuki Sato , Takayasu Sakurai , Kazuhiro Sawada , Tsukasa Shirotori
DOI: 10.1109/ESSCIRC.1988.5468419
关键词:
摘要: The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA with typical ADDRESS to HIT delay, the largest size and fastest speed ever reported as an memory[1]. device integrates data/instruction memory, tag comparator on chip. It serves several host MPUs by aluminum masterslice.
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