Transceiver including a high latency communication channel and a low latency communication channel
作者： Mehdi Khanpour , Jun Cao , Afshin Momtaz , Chang Liu , Heng Zhang
DOI:
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摘要: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes high communication channel low that is configured to be bypass channel. The may utilized when implementing used applications. By bypassing channel, introduced therein (due many stages of de-serialization reduce data rate digital processing) can avoided. An increase realized pass data. delay-locked loop (DLL) phase align transmitter clock with receiver compensate limited tolerance offset between these clocks.
lens.org 参考文章(25)
Bijit T. Patel, Multi-function bypass port and port bypass circuit ,(2004)
Ian Swarbrick, Joseph Jun Cao, Chip-to-chip communications ,(2013)
Yannick Bonhomme, Valentin Gherman, Method and device for controlling the latency of electronic circuits ,(2011)
Mehmet Tazebay, Scott Powell, Method and system for self-adapting dynamic power reduction mechanism for physical layer devices in packet data networks ,(2011)
Stuart F. Oberman, Rodney N. Mullendore, Kamran Malik, Anil Mehta, Dynamic selection of lowest latency path in a network switch ,(2001)
Jeremy Chatwin, System and method for implementing a phase detector to support a data transmission procedure ,(2007)
Anthony Bessios, Jared L. Zerbe, Vladimir M. Stojanovic, Andrew C. C. Ho, Mark A. Horowitz, Bruno W. Garlepp, Grace Tsang, Jason C. Wei, Partial response receiver ,(2004)
Kevin D. Howard, Apparatus for enhancing performance of a parallel processing environment, and associated methods ,(2010)
Koray Oner, Packet manager interrupt mapper ,(2003)
Pantas Sutardja, Lei Wu, Hongying Sheng, Architectures, circuits, systems and methods for reducing latency in data communications ,(2003)