An on chip low skew optical clock receiver

摘要: Clock distribution across a digital chip raises several serious issues in current and future integrated circuit technology. The of clocks with frequencies the giga-hertz range is di cult because interconnect parasitics. skew due to variation sources becoming control traditional balanced networks. Optical interconnects are currently being evaluated as technique distribute clock signal throughout chip. Optics provides potential for very low distribution. This thesis presents design an optoelectric receiver operating at 1 GHz. has been simulated successfully full layout completed. impact from input signal, process, environment have evaluated. Process found contribute most skew. A strategy prepared testing fabricated result simulation fully functional CMOS optical 0.18 m technology Thesis Supervisor: Duane Boning Title: Associate Professor Electrical Engineering Computer Science