Fabrication of a non-ldd graded p-channel mosfet

摘要: A transistor and fabrication method are presented in which a graded junction is formed using plurality of source/drain dopant implants. The implants performed such that higher concentrations species implanted at lower energies energies. In an embodiment, anneal step used to create the by exploiting concentration dependence diffusivity (i.e., regions high more mobile than low concentration). Sub-0.25-micron transistors process described herein may be less susceptible deleterious capacitive loading parasitic resistance having conventionally lightly doped drain Transistors according this application also advantageously include highly shallow junctions while incorporating deeper avoid problem spiking. Integrated circuits including further subject inter-transistor variation effective channel length, therefore threshold voltage roll-off drive current variability, integrated transistors.