Logic circuit and design method for improved testability

摘要: A method for designing integrated circuits improved testability. main logic function operable in initialization and test modes is defined terms of component macros. Testability circuitry generating CLEAR, CLEAR0 CLEAR1 testability signals also defined. The CLEAR have the first state during system operation mode, second states equal amounts time mode. most remainder First-type macros, such as multiplexers having Select or other inputs requiring are identified. Second-type macros flip flops clear, set mode Third-type Enable Interconnections between identified first, third-type associated Both timing simulations analysis on circuit can then be performed before redefined.