Reduction operations in parallel discrete event simulations

摘要: Building on Reynolds's hardware/software framework for parallel discrete event simulation (PDES), we establish a number of novel and best known results based the use reduction-based computing to support PDES. We demonstrate utility spectrum well-known PDES synchronization protocols, such as conservative techniques Time Warp. We enhance hardware portion this at three levels: (1) define virtual computation model, (2) develop functional design, (3) present detailed implementation design. Each preceding steps is correctness criteria here. algorithms performing message acknowledgments. prove one them, single phase acknowledgment algorithm that takes advantage existence global time. Finally, introduce target-specific reductions, very promising strategy disseminating near-perfect state information in PDES's. A reduction where each logical process receives (reduced values) only from those processes which it logically dependent. values can have sub-quadratic sequential time complexity. Supporting empirical clearly reductions will provide significant space savings