Achieving High Instruction Cache Performance With An Optimizing Compiler

摘要: Increasing the execution power requires a high instruction issue bandwidth, and decreasing encoding applying some code improving techniques cause expansion. Therefore, memory hierarchy performance has become an important factor of system performance. An placement algorithm been implemented in IMPACT-I (Illinois Microarchitecture Project using Advanced Compiler Technology - Stage I) C compiler to maximize sequential spatial localities, minimize mapping conflicts. This approach achieves low cache miss ratios traffic for small, fast caches with little hardware overhead. For ten realistic UNIX* programs, we report (average 0.5%) 8%) 2048-byte, direct-mapped 64-byte blocks. result compares favorably fully associative results reported by other researchers. We also present effect size, block sectoring, partial loading on The optimization is shown be stable across architectures different density.