Implementation of encryption algorithms on transport triggered architectures
作者： P Hamalainen , M Hannikainen , T Hamalainen , Henk Corporaal , J Saarvinen
DOI: 10.1109/ISCAS.2001.922340
关键词:
摘要: The paper studies a configurable processor architecture, transport triggered architecture (TTA), for encryption algorithm implementations. automatic TTA design space exploration is applied and configurations with good cost-performance ratio are found. It shown that TTAs at least equal to commercial processors in performance. According earlier the performance level also achieved far lower cost. This encourages further development tuned functionality.
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