Method and apparatus for optimizing cache hit ratio in non L1 caches

作者: Michael Joseph Azevedo , Andrew Dale Walls

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摘要: A method and apparatus for increasing the performance of a computing system hit ratio in at least one non-L1 cache. caching assistant processor are embedded processing system. The analyzes activity, monitors coordinates data requests from processor, processors other accessing devices, accesses throughout cache hierarchy. is provided with dedicated storing fetched prefetched data. improves by anticipating which likely to be requested next, that an appropriate prior being or devices. includes analyzing activity optimizing performs caches monitoring determine knowledge program code currently processed if patterns accession exist. Based upon gained through accession, anticipates future requests.

参考文章(44)
David Scott Ray, Francis Patrick O'Connell, Michael John Mayfield, Cache prefetching of L2 and L3 ,(1999)
Jeffrey Harris Dreibelbis, Thomas James Heller, Michael Ignatowski, Wayne Frederick Ellis, Howard Leo Kalter, David Meltzer, Multi-port multiple-simultaneous-access DRAM chip ,(1997)
Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Richard Weiss, Paul Lowney, Profile-guided stride prefetching ,(2001)
Sebastian Theodore Ventrone, Wilbur David Pricer, Clarence Rosser Ogilvie, Kenneth Joseph Goodnow, Apparatus and method for prefetching data based on information contained in a compiler generated program map ,(1997)
Robert A. Cargnoni, Dale R. Greenley, David R. Stiles, Harold L. McFarland, Korbin S. Van Dyke, Shrenik Mehta, John Gregory Favor, Method and apparatus for executing string instructions ,(1998)