Exploiting fine- and coarse-grain parallelism in embedded programs

摘要: Due to the technological advances, mapping of embedded applications onto single-chip multi-processor systems becomes a feasible and very interesting option. What is needed an environment that supports designer in transforming algorithmic specification into suitable parallel implementation. In this paper we present results our experiments with one such environment, which developed within laboratory. As opposed existing ones, framework semi-automatically exploits different kinds coarse fine-grain parallelism from program written ANSI C. It employs functional pipelining data set partitioning simultaneously source-to-source transformations obtain most advantageous hierarchical parallelizations. This combination high speedups for all tested benchmarks.