Industrial experience with test generation languages for processor verification

作者: Michael Behm , John Ludden , Yossi Lichtenstein , Michal Rimon , Michael Vinov

DOI: 10.1145/996566.996578

关键词:

摘要: We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease expressing complex tasks. cost benefit are demonstrated: training takes up to six months; simulation time required desired level coverage has decreased by factor twenty; number escape bugs been reduced.

参考文章(12)
Samir Palnitkar, Design Verification with e ,(2003)
E. Bin, R. Emek, G. Shurek, A. Ziv, Using a constraint satisfaction formulation and solution techniques for random test program generation Ibm Systems Journal. ,vol. 41, pp. 386- 402 ,(2002) , 10.1147/SJ.413.0386
Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv, User defined coverage—a tool supported methodology for design verification design automation conference. pp. 158- 163 ,(1998) , 10.1145/277044.277081
J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus, D. J. Klema, T. N. Le, F. D. Lewis, P. E. Milling, L. A. McConville, B. S. Nelson, V. Paruthi, T. W. Pouarz, A. D. Romonosky, J. Stuecheli, K. D. Thompson, D. W. Victor, B. Wile, Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems Ibm Journal of Research and Development. ,vol. 46, pp. 53- 76 ,(2002) , 10.1147/RD.461.0053
Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, Gil Shurek, Test program generation for functional verification of PowerPC processors in IBM design automation conference. pp. 279- 285 ,(1995) , 10.1145/217474.217542
F. Carbognani, C.K. Lennard, C.N. Ip, A. Cochrane, P. Bates, Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard design, automation, and test in europe. pp. 20088- 20094 ,(2003) , 10.1109/DATE.2003.1186677
A. Adir, E. Almog, L. Fournier, E. Marcus, M. Rimon, M. Vinov, A. Ziv, Genesys-Pro: innovations in test program generation for functional processor verification IEEE Design & Test of Computers. ,vol. 21, pp. 84- 93 ,(2004) , 10.1109/MDT.2004.1277900
A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, V. Schwartzburd, Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator IBM Systems Journal. ,vol. 30, pp. 527- 538 ,(1991) , 10.1147/SJ.304.0527
Bernd-Holger Schlingloff, Edmund M. Clarke, Model Checking ,(1999)