Towards a Better Indicator for Cache Timing Channels.

摘要: Recent studies highlighting the vulnerability of computer architecture to information leakage attacks have been a cause significant concern. Among various classes microarchitectural attacks, cache timing channels are especially worrisome since they potential compromise users' private data at high bit rates. Prior works demonstrated use miss patterns detect these attacks. We find that traces can be easily spoofed and thus may not able identify smarter adversaries. In this work, we show \emph{cache occupancy}, which records number blocks owned by specific process, leveraged as stronger indicator for presence channels. observe modulation access latency in recognized through analyzing pairwise occupancy patterns. Our experimental results cannot obfuscated even advanced adversaries successfully evade miss-based detection.