Processor core to coprocessor interface with FIFO semantics

摘要: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, first processor initiates content transfer into the FIFO. The activates signal that is reserved indicating resides within A second accepted. causes be deactivated. This exchange of demarcates FIFO transaction, which mediated by interface circuitry