Parameter variation tolerant method for circuit design optimization

摘要: A method for optimizing the design of a chip or system by decreasing cost function that encompasses plurality constraints in presence variations parameters is described. The makes use numerical optimization, simulated annealing, any other objective-driven optimization means, and accounts uncertainties modeling variables functions. significant reduction number which are violated at end an process achieved, even when all cannot be satisfied. also reduces cycle time operates limits increase minimum operational particular implementation modeled unpredictable delay introduced elements design. includes steps of: defining objective computed from functions system; deriving merit adding to it separation terms; minimizing expected value confronted with