Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating
作者： Hans-Werner Tast , Ralf Winkelmann , Christian Habermann , Matthias Pflanz , Christian Jacobi
DOI:
关键词:
摘要: A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The comprises choosing at least one master seed to determine initial values as initialization said and/or stimuli data interface of circuit, two different configurations every chosen seed, executing functional simulation with configuration by determined based on corresponding comparing results simulations against each other executed configurations, reporting an error if are not identical.
lens.org 参考文章(8)
Markus Danninger, Theodor Kupfer, Paul Presslein, Modification of error statistics behind equalizer to improve inter-working with different FEC codes ,(2007)
Franco Motika, Leendert M. Huisman, Leah M. Pfeifer Pastel, William V. Huott, Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection ,(2003)
John Teife, Rajit Manohar, Programmable asynchronous pipeline arrays field-programmable logic and applications. pp. 345- 354 ,(2004) , 10.1007/978-3-540-45234-8_34
Darren Bertanzetti, Control of clock gate cells during scan testing ,(2007)
Yutaka Tamiya, Verification support apparatus, verification support method, and computer product ,(2009)
Hans Mikael Jacobson, Matthew Earl Fernsler, Johny Srouji, Todd Swanson, Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design ,(2008)
Robert A. Alfieri, Robert J. Hasslen, Watchdog monitoring for unit status reporting ,(2006)
David James Mielke, Gayvin E Stong, Systems and methods for performing clock gating checks ,(2002)