Block-level added redundancy explicit authentication for parallelized encryption and integrity checking of processor-memory transactions

摘要: The bus between the System on Chip (SoC) and external memory is one of weakest points computer systems: an adversary can easily probe this in order to read private data (data confidentiality concern) or inject integrity concern). conventional way protect against such attacks ensure implement two dedicated engines: performing encryption another authentication. This approach, while secure, prevents parallelizability underlying computations. In paper, we introduce concept Block-Level Added Redundancy Explicit Authentication (BL-AREA) describe a Parallelized Encryption Integrity Checking Engine (PE-ICE) based concept. BL-AREA PE-ICE have been designed provide effective solution both security services allowing for full parallelization processor write operations optimizing hardware resources. Compared standard which ensures only confidentiality, show that additionally guarantees code less than 4% run-time performance overhead.