A 3-V Wideband CMOS Switched-Current A/D-Converter

摘要: The simulated and measured performance of an experimental wideband CMOS A/D converter design is presented in this chapter. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture order evaluate the technique for digital radio applications. With f = 1.83 MHz, SFDR 60.3 dB SNDR 46.5 at s 3 MHz. Although V was fabricated standard 5 V, 0.8 μm process, high bandwidth achieved. Since ADC maintains ≥ 40 input frequencies more than 20 it has highest reported any A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared other converters found competitive also respect area power efficiency.