摘要: This paper focuses on static timing analysis in the presence of capacitive coupling. We propose a novel gate delay model, dynamically bounded model. In contrast to min-max or model which assumes fixed range, [dmin, dmax], for each circuit component, our new allows specification variations and conditions upon will hold. Novel algorithms can thus bound delays. To demonstrate effectiveness this approach, we use perform critical path Our experiments show that approach avoids pessimism when compared PERT assuming worst case
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