Leakage proof and noise tolerant domino circuit based on SEFG
作者： Jinhui Wang , Na Gong , Ligang Hou , Xiaohong Peng , Wuchen Wu
DOI: 10.1109/ICSICT.2010.5667418
关键词:
摘要: Utilizing the sleep switch transistor technique and dual threshold voltage technique, a source following evaluation gate (SEFG) based domino circuit is presented in this paper for simultaneously suppressing leakage current enhancing noise immunity. Simulation results show that of proposed design can be reduced by 43%, 62%, 67% while improving 19.7%, 3.4 %, 12.5% margin as compared to standard low circuit, SEFG structure, respectively. Also, inputs clock signals combination static state dependent characteristic analyzed minimum states different AND gates are obtained.
sci-hub.se 参考文章(4)
J.T. Kao, A.P. Chandrakasan, Dual-threshold voltage techniques for low-power digital circuits IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 1009- 1018 ,(2000) , 10.1109/4.848210
Na Gong, Baozeng Guo, Jianzhong Lou, Jinhui Wang, Analysis and optimization of leakage current characteristics in sub-65nm dual Vt footed domino circuits Microelectronics Journal. ,vol. 39, pp. 1149- 1155 ,(2008) , 10.1016/J.MEJO.2008.01.028
Z. Liu, V. Kursun, Leakage Biased pMOS Sleep Switch Dynamic Circuits IEEE Transactions on Circuits and Systems Ii-express Briefs. ,vol. 53, pp. 1093- 1097 ,(2006) , 10.1109/TCSII.2006.882206
Blaine Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul Gronowski, Dan Krueger, Charles Morganti, Steve Troyer, A 65 nm 2-Billion Transistor Quad-Core Itanium Processor IEEE Journal of Solid-state Circuits. ,vol. 44, pp. 18- 31 ,(2009) , 10.1109/JSSC.2008.2007150