Method and apparatus for power control in devices
作者： Frederick A. Ware , Matthew M. Griffin , Mark A. Horowitz , Richard M. Barth , James A. Gasbarro
DOI:
关键词:
摘要: A power control circuit to minimize consumption of CMOS circuits by disabling/enabling the clock input circuit. phase locked loop (PLL) or delay (DLL) drives a capacitive load component and dummy comparable load. standby latch is provided component. In state, signal not but PLL/DLL continues operate, driving Thus, when it desirable on circuit, reset component, thereby turning with little latency.
lens.org 参考文章(21)
Peter Deane, Low power dual-mode CMOS bias voltage generator ,(1987)
Shoji Matsubara, Memory integrated circuit with an improved stand-by mode control circuit ,(1988)
Andreas Fritz, Joerg Pollmann, Hartmut Hantsch, Integrated circuit with logic portion and control input(s) - has evaluating circuit, coupled to logic portion and control input(s), for determining state of supply voltage ,(1991)
Masashi Deguchi, Toshimichi Matsuzaki, Low power consumption microprocessor ,(1991)
Aurav Gollabinnie, Brian Verstegen, Rashid N. Khan, Win-Sheng Cheng, Chien-Feng Cheng, Cheng Chen, Sleep mode refresh apparatus ,(1989)
Lavaughn F. Jr. Watts, Steven J. Wallace, Real-time power conservation for portable computers ,(1990)
Hideaki Yokouchi, Method and apparatus for reduced power integrated circuit operation ,(1991)
Darren J. Cepulis, Paul M. Garner, Robert Richard Carter, Caroline A. Boone, Apparatus for reducing computer system power consumption ,(1989)
Rune Lindholm, Sirpa Korhonen, Clock frequency adjustment of an electrical circuit ,(1992)