Architectures and VLSI implementations of the AES-Proposal Rijndael
作者： N. Sklaos , O. Koufopavlou
关键词:
摘要: Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative operated both for encryption decryption process. They reduce required hardware resources achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic reaches a throughput value equal to 259 Mbit/sec. It performs efficiently applications with low covered area resources. second architecture optimized performance using pipelined technique. Its can reach 3.65 Gbit/sec.
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Mititada Morisue, Kiyomichi Araki, Ikuo Fujita, Fast Inverters over Finite Field Based on Euclid's Algorithm IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. ,vol. 72, pp. 1230- 1234 ,(1989)
Bruce Schneier, Applied cryptography (2nd ed.): protocols, algorithms, and source code in C John Wiley & Sons, Inc.. ,(1995)
Kris Gaj, Pawel Chodowiec, Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. AES Candidate Conference. pp. 40- 54 ,(2000)
Andreas Dandalis, Viktor K. Prasanna, Jose D.P. Rolim, A Comparative Study of Performance of AES Final Candidates Using FPGAs cryptographic hardware and embedded systems. pp. 125- 140 ,(2000) , 10.1007/3-540-44499-8_9
P. Mroczkowski, Implementation of the block cipher Rijndael using Altera FPGA Journal of telecommunications and information technology. pp. 80- 86 ,(2001)
Bruce Schneier, Phil Sutherland, Applied Cryptography: Protocols, Algorithms, and Source Code in C ,(1993)
Wang, Troung, Shao, Deutsch, Omura, Reed, VLSI Architectures for Computing Multiplications and Inverses in GF(2 m ) IEEE Transactions on Computers. ,vol. 34, pp. 709- 717 ,(1985) , 10.1109/TC.1985.1676616
H. Brunner, A. Curiger, M. Hofstetter, On computing multiplicative inverses in GF(2/sup m/) IEEE Transactions on Computers. ,vol. 42, pp. 1010- 1015 ,(1993) , 10.1109/12.238496
A.J. Elbirt, W. Yip, B. Chetwynd, C. Paar, An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists IEEE Transactions on Very Large Scale Integration Systems. ,vol. 9, pp. 545- 557 ,(2001) , 10.1109/92.931230
Kris Gaj, Pawel Chodowiec, Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays the cryptographers track at the rsa conference. pp. 84- 99 ,(2001) , 10.1007/3-540-45353-9_8