Combined write-operand queue and read-after-write dependency scoreboard

摘要: In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in source queue destination queue. An execution unit successively obtains of the queue, initiates operation upon specifiers, reads specifier retires result at specified destination. Read-after-write conflicts may occur because overlap plurality instructions. Just prior to beginning current instruction, is checked for conflict between previously issued but not yet retired When execution, its are marked indicate that they associated with executed instruction. preferred construction, each entry has "write pending" bit cleared during flush when read pointer incremented. issue identifies next be issued, so write-pending set Each two comparators enabled by detect specifiers.