Internetworking device with enhanced protocol translation circuit

作者: Jonathan M. Parlan , Shashi Kumar

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摘要: A special memory overlay circuit uses a first DRAM buffer in combination with second faster SRAM to reduce the time required translate information into different network protocols. Packet data is stored and packet headers requiring manipulation are memory. Because has access than memory, processor can reformat header protocols shorter amount of time. also use relatively small compared remaining data. Since only used for storing headers, little additional cost utilize while substantially increasing performance.

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