Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses

摘要: An electronic computer system including a central processor and hierarchical memory having large relatively low speed random access small high set-associative cache data store section for storing lines of from the directory indicating, by means line identifier fields at any time, currently resident in cache, is provided with way to improve distribution across congruence classes within cache. A mechanism performing permutation operation on an M bit portion (X) address, which determines class into address will map. The performs bit-matrix multiplication said M-bit M×M matrix (where real positive integer greater than 1) produce permuted (X'). controls utilize (X') determine given automatically subsequent if one identifiers identifies, every member stored directory, matches field request CPU. If match successful accessed requested specified