Advances in electronic testing : challenges and methodologies

摘要: Foreword by Vishwani D. Agrawal Preface Dimitris Gizopoulos Contributing Authors Dedication Chapter 1-Defect-Oriented Testing Robert C. Aitken 1.1 History of Defect-Oriented 1.2 Classic Defect Mechanisms 1.3 in Advanced Technologies 1.4 Defects and Faults 1.5 Test Types 1.6 Experimental Results 1.7 Future Trends Conclusions Acknowledgments References 2-Failure Nanometer Jaume Segura, Charles Hawkins Jerry Soden 2.1 Scaling CMOS Technology 2.2 Failure Modes 2.3 Methods for ICs 2.4 Conclusion 3-Silicon Debug Doug Josephson Bob Gottlieb 3.1 Introduction 3.2 Silicon 3.3 Process 3.4 Flow 3.5 Circuit Failures 3.6 A Case Study 3.7 Challenges 3.8 Acknowledgements 4-Delay Adam Cron 4.1 4.2 Delay Basics 4.3 Application 4.4 Details 4.5 Vector Generation 4.6 Chip Design Constructs 4.7 ATE Requirements 4.8 Conclusions: Tests vs. 5-High-Speed Digital Interfaces Wolfgang Maichen 5.1 New Concepts 5.2 Techniques 5.3 Characterization Modeling 5.4 Outlook 6-DFT-Oriented, Low-Cost Testers Al Crouch GeirEide 6.1 6.2 Cost - the Chicken Low Tester 6.3 Use Models 6.4 Why When is DFT Cost? 6.5 What does have to do with Tester? 6.6 Life, Universe, Everything Recommended Reading 7-Embedded Cores System-on-Chip Rubin Parekhji 7.1 Embedded SOCs 7.2 Paradigm 7.3 7.4 Access 7.5 ATPG 7.6 SOC 7.7 At-speed 7.8 Memory Logic BIST 7.9 8-Embedded R. Dean Adams 8.1 8.2 The Under 8.3 8.4 Patterns 8.5 Self 8.6 Memories & 8.7 9-Mixed-Signal DfT Stephen Sunter 9.1 Brief 9.2 State Art 9.3 Advances Last 10 Years 9.4 Emerging Directions 9.5 EDA Tools Mixed-Signal 9.6 10-RF Randy Wolf, Mustapha Slamani, John Ferrario Jayendra Bhagat 10.1 10.2 RF 10.3 Reduction Factors 10.4 Hardware 10.5 Development 10.6 High Frequency Simulation 10.7 Device Interface 10.8 11-Loaded