FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
作者： Roland Höller
DOI: 10.1007/978-3-540-45234-8_95
关键词:
摘要: This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The network interface node one hand provides all necessary hardware to be flexibly used in broad range applications. switch add-on other accounts for packet delay uncertainties switches is crucial synchronization.
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