作者: Phillip Anthony Carswell , Kerry Lucille Johns-Vano , Ty Bao Lien , William Louis Perea , David Michael Harrison
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摘要: A configurable cryptographic processing engine (100) provides high performance support for symmetric combiner type algorithms. As many as two independent algorithms may be performed at the same time through processes of background staging and algorithm multi-tasking. 3-stage instruction pipeline, dynamically co-processor (550), 32-bit RISC based architecture on order 60 Mbps aggregate throughput.