Delay-locked loop having a pre-shift phase detector
作者： Kang Yong Kim
DOI:
关键词:
摘要: A clock generator for generating an output signal synchronized with input having first and second adjustable delay lines. The lines is adjusted following initialization of the to expedite obtaining a lock condition initialization. line after synchronization achieved line, or when reaches maximum delay. reset initially obtained, compensate resetting line.
google.de 参考文章(67)
Wataru Sakamoto, Semiconductor device including clock generation circuit capable of generating internal clock stably ,(2000)
Monte F. Mar, Adjustable lock detector for a phase-locked loop circuit ,(1996)
Katsunori Sawai, Yukihiko Shimazu, Clock generating circuit, PLL circuit, semiconductor device, and methods for designing and making the clock generating circuit ,(1996)
Elie Torbey, Digital phase-locked loop circuit with reduced phase jitter frequency ,(2000)
Alexander Waizman, Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle ,(1993)
Katsushi Konno, Differential delay line clock generator ,(1994)
Kazuo Tateishi, Power generating installation ,(1997)
Scott W. Alvarez, Hansel A. Collins, David P. Chengson, Edward C. Priest, System and method to reduce jitter in digital delay-locked loops ,(1996)
James E. Miller, Low pass filters in DLL circuits ,(2003)
Philip M. Freidin, Charles R. Erickson, Kerry M. Pierce, Phase-locked delay loop for clock correction ,(1996)