Receiver clock test circuitry and related methods and apparatuses
作者： Kunal Desai , Srinivasaraman Chandrasekaran
DOI:
关键词:
摘要: An integrated circuit includes a plurality of receivers, each having clock and data recovery circuit. A first local in receiver can be caused to produce test which simulates condition tested, while second the receivers that is use place reference receiving sequence at its input. The circuits include control loops responsive loop signals modify selected generate response selective one (i) corresponding signal for normal operation or during test, (ii) applied case produced.
lens.org 参考文章(35)
Jun Cao, Afshin Momtaz, Built-in self-test for multi-channel transceivers without data alignment ,(2004)
Peter Ho, Circuits and methods for clock and data recovery ,(2008)
Mickael Joulaud, Stephanie a. Palmier, Robert A. Hayes, Thibault J B Roques-Carmes, Display Device Based on Electrowetting Effect ,(2005)
Xicheng Jiang, Aaron W. Buchwald, Myles Wakayama, Howard A. Baumer, Avanindra Madisetti, Jurgen Van Engelen, Michael Le, Hui Wang, Phase interpolator device and method ,(2004)
Brian Leibowitz, Jaeha Kim, Hae-Chang Lee, Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement ,(2008)
Jared L. Zerbe, Vladimir M. Stojanovic, Fred F. Chen, Selectable-tap equalizer ,(2008)
Kurt Chan, Alistair D. Black, Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost ,(2003)
Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei, An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery international solid-state circuits conference. pp. 468- 628 ,(2008) , 10.1109/ISSCC.2008.4523260
S. Sidiropoulos, M.A. Horowitz, A semidigital dual delay-locked loop IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 1683- 1692 ,(1997) , 10.1109/4.641688