An implementation of the Zer o Instruction Set Computer (ZISC036) on a PC/ISA-bus card
作者： A. Eide , G. Szekely , A. Minerskjold , T. Lindblad , C. S. Lindsey
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摘要: An implementation of the new IBM Zero Instruction Set Computer (ZISC036) on a PC/ISA-bus card is reported. This circuit has 36 processing elements type similar to that Radial Basis Function or RBF-like neurons. It highly parallel and cascadeable building block with on-chip learning capability, well suited for pattern recognition, signal processing, etc. A two ZISC036 was built tested noisy character recognition "benchmark". Some future implementations ideas are presented.
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