作者: Y. Ono , Y. Takahashi , K. Yamazaki , M. Nagase , H. Namatsu
DOI: 10.1109/16.817580
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摘要: A new fabrication method for Si single-electron transistors (SETs) is proposed. The applies thermal oxidation to a wire with fine trench across it on silicon-on-insulator substrate. During the oxidation, converted, in self-organized manner, into twin SET structure two islands, one along each edge of trench, due position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that can operate as individual SET's. Since present produces SET's same time tiny area, suitable integrating logic circuits based pass-transistor type and CMOS-type logic, which promises lead LSIs.