作者: Dan H. Wolaver , Daniel C. Upp
DOI:
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摘要: An SRTS clock recovery apparatus and method are provided. The broadly includes a controllable destination node generator (37) such as digitally oscillator, block (36, 38, 40) for generating local RTS-related value from the system reference (10), comparator (50) which compares incoming to provide feedback error or control signal is used adjust (37). If desired, filter (52) filters can be provided in loop. With loop provided, when faster than source clock, will cause slow, vice versa.