Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

作者: Farzan Fallah , Massoud Pedram

DOI: 10.1093/IETELE/E88-C.4.509

关键词:

摘要: … on circuit optimization and design automation techniques to … describes a number of circuit optimization techniques for … the circuit speed requirements while saving the energy used for the …

参考文章(33)
Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2 international symposium on low power electronics and design. pp. 213- 218 ,(2002) , 10.1145/566408.566460
David Nguyen, Abhijit Davare, Michael Orshansky, David Chinnery, Brandon Thompson, Kurt Keutzer, Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03. pp. 158- 163 ,(2003) , 10.1145/871506.871545
Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong, An MTCMOS design methodology and its application to mobile computing Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03. pp. 110- 115 ,(2003) , 10.1145/871506.871536
Dongkun Shin, Jihong Kim, Seongsoo Lee, Low-energy intra-task voltage scheduling using static timing analysis Proceedings of the 38th conference on Design automation - DAC '01. pp. 438- 443 ,(2001) , 10.1145/378239.378551
L.S. Nielsen, C. Niessen, J. Sparso, K. van Berkel, Low-power operation using self-timed circuits and adaptive scaling of the supply voltage IEEE Transactions on Very Large Scale Integration Systems. ,vol. 2, pp. 391- 397 ,(1994) , 10.1109/92.335008
R. Gonzalez, B.M. Gordon, M.A. Horowitz, Supply and threshold voltage scaling for low power CMOS IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 1210- 1216 ,(1997) , 10.1109/4.604077
Yuan Taur, D.A. Buchanan, Wei Chen, D.J. Frank, K.E. Ismail, Shih-Hsien Lo, G.A. Sai-Halasz, R.G. Viswanathan, H.-J.C. Wann, S.J. Wind, Hon-Sum Wong, CMOS scaling into the nanometer regime Proceedings of the IEEE. ,vol. 85, pp. 486- 504 ,(1997) , 10.1109/5.573737
Mohab Anis, Mohamed Mahmoud, Mohamed Elmasry, Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique design automation conference. pp. 480- 485 ,(2002) , 10.1145/513918.514041
K.M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S.K.H. Fung, J.X. An, B. Yu, C. Hu, BSIM4 gate leakage model including source-drain partition international electron devices meeting. pp. 815- 818 ,(2000) , 10.1109/IEDM.2000.904442
Tadahiro Kuroda, Takayasu Sakurai, Fumitoshi Hatori, Tetsuya Fujita, Variable Threshold-Voltage CMOS Technology IEICE Transactions on Electronics. ,vol. 83, pp. 1705- 1715 ,(2000)