Nanoelectronic and Nanophotonic Interconnect

摘要: A significant performance limitation in integrated circuits has become the metal interconnect, which is responsible for depressing on-chip data bandwidth while consuming an increasing percentage of power. These problems will grow as wire diameters scale down and resistance-capacitance product interconnect wires increases hyperbolically, threatens to choke off computational chips that we have come expect over time. We examine some quantitative implications these trends by analyzing International Technology Roadmap Semiconductors. compare potential replacing global electronic future with a photonic see there principle four order magnitude bandwidth-to-power ratio advantage latter. This indicates it could be possible dramatically improve chip without scaling transistors but rather utilize capability existing much more efficiently. However, at this time not clear if advantages can realized. discuss various issues related architecture components necessary implement interconnect.